SAYEEKUMAR
@sayeekumar332
CISMA CONSULTANTS PVT LTD
Chennai
1
Followers
2
Following
13
Public Repos
0
Private Repos
Language Breakdown
Lines of code distribution across 8 owned repositories
5.9M
Total LOC
Verilog
5,847,243 lines
98.6%
N/A
Java
26,431 lines
0.4%
N/A
Makefile
20,313 lines
0.3%
N/A
C
20,052 lines
0.3%
N/A
SystemVerilog
8,757 lines
0.1%
N/A
Other
6,680 lines
0.1%
N/A
I
I-Shaped Developer
I-shapedSpecialist — deep expertise in Verilog
Verilog
Java
Makefile
C
SystemVerilog
Collaboration Network
Global Impact visualization
Repos
15
PRs
0
Growth
+18%
Top Collaborators
No collaborator data yet.
Coding Streak
Contribution activity over the past year
1 day
27
Contributions
13
Commits
5
Pull Requests
Jun
Jul
Aug
Sep
Oct
Nov
Dec
Jan
Feb
Mar
Apr
May
Jun
Mo
We
Fr
Based on GitHub activity
Less
More
Followers
1
Top Repositories
PROCESSOR-MICROARCHITECTURE
This is a repository exclusively created for providing open source verilog codes for various processor microarchitectures and various programming language based codes for research purpose
2
0
Verilog
ws-eng-event-ticketing-assessment
Real Work coding assessment
0
0
ws-eng-conduit-ai-assessment
0
0
instruction_decoder
instruction_decoder
0
0
sayeekumar_swaminathan_RTL
0
0
SystemVerilog
phinity_static_branch_predictor
0
0
verilog_uart_testing
This is a repo that has to be tested by Phinity
0
0
forage-jpmc-swe-task-1
Starter repo for task 1 of the JPMC software engineering program
0
0
Python
SAPHMP
0
0
RISCV-with-CNN-coprocessor
0
0
Verilog
Open Source Impact
Contributions to external projects
3 merged PRs
Contributed to 2 repositories